1. Field of the Invention
This invention relates in general to a comparator cell for analog-to-digital flash converters and, more particularly, to a comparator cell that reduces power dissipation and peak voltage drop across a load while improving accuracy.
2. Background Art
Circuitry for converting analog signals into corresponding equivalent digital signals has a multiplicity of uses in present day instrumentation and telemetry equipment. When all bits of the digital output are determined simultaneously from the analog voltage, the method is referred to as the parallel method or flash encoding method. This method refers to a plurality of parallel comparators wherein each comparator is responsive to the analog voltage attaining a predetermined voltage level.
A flash encoding converter has 2.sup.N digital output states for an N-bit encoder where N is a predetermined integer. A peak analog voltage is divided into 2.sup.N levels wherein each level is represented by one of the digital output states representable with an N bit digital word. A conventional N-bit encoder requires 2.sup.N -1 comparators which is prohibitive when N is large (i.e., six). Furthermore, the output from the parallel bank of voltage comparators is in the form of 2.sup.N -1 binary data signals. These outputs are typically encoded to N bits of binary information by conversion logic. This requires a prohibitively large number of elements in the conversion logic.
One known flash analog-to-digital converter that overcomes these disadvantages is described in U.S. Pat. No. 4,386,339 which is incorporated herein by reference. This referenced patent provides a direct flash converter having a comparator cell with independent parallel analog-to-digital encoders for each bit. Each independent bit-encoder has cross-coupled level sensors coupled to a single comparator such that the output of the comparator is a directly encoded compact binary output. Thus, only one comparator is required for each bit, and the need for conversion logic is eliminated, resulting in a practical, direct multi-bit flash converter. For even larger values of N, some conversion is required, but still less than with conventional techniques.
However, these cross-coupled level sensors comprise differentially coupled transistor pairs wherein one base is coupled for receiving an analog input signal and the other base is coupled for receiving a threshold voltage. The collectors on each side of each level sensor are coupled together, alternately directly coupled and cross-coupled to form two collector current paths. These two current paths, in turn, are each tied to one of the emitters of a pair of transistors whose bases are commonly tied. The current through these two current paths is directed through two load resistors having equal resistance which provides a voltage differential as an output of the comparator cell. For each comparator cell containing an even number of level sensors, a current source is coupled to the emitter of one of the pair of transistors for providing additional current to one of the current paths. This additional current source increases power dissipation of the circuit, requires alpha compensation circuitry, produces additional load voltage drop and therefore a larger supply voltage, and decreases accuracy since errors in the current source current are reflected back as errors in the level sensor.
Thus, a need exists for an improved flash converter having a comparator cell that has decreased power dissipation, increased accuracy, requires a lower supply voltage, and does not require additional circuitry for alpha compensation.